Schematic of JTAG and serial-over-USB

As previously mentioned, the EPCS will take advantage of the FTDI FT2232H USB-serial converter and its integrated multi-protocol synchronous serial engine (MPSSE) support for JTAG for programming and debugging the ADuC7025 firmware. The second serial port provided by the FT2232H will be used in UART mode to provide a link for streaming data back to a PC. I envision two uses of this UART:

1. The UART communicates via a RS-232 level converter and standard DB-9 connector to act as a generic USB-serial adapter attaching any RS-232 device to the PC. Simultaneously, the ADuC7025 snoops the streaming traffic, transparent to both endpoints. This enables aggregating the serial data with local ADC measurements using a single time source, streamlining later time alignment of different sensors.
2. The UART may alternatively be used for bidirectional communication between the ADuC7025 and PC at high speed.

Since the FT2232H has two ports, creative use of tri-state buffers could allow both these modes of operation simultaneously when not debugging, but I do not feel this would be worth the added complexity. Instead we will focus on preventing leakage currents from flowing through the ground connection established by the USB cable.

To prevent leakage currents it is desirable to keep the EPCS main circuitry isolated from ordinary electronics (anything connected to the power grid without a medical grade power supply). The UART is straightforward to isolate -- it has only two unidirectional data lines and moderate baud rate. I simply interposed an ADUM2201 "IEC60601-1 compliant digital isolator" and voilà, problem solved.

JTAG presents a little more severe problem for isolation, as there are both more pins and higher frequency signals, so that inclusion of a digital isolator would have a significant detrimental impact on the debugging experience. At the same time, firmware loading and debugging is not part of the intended use of the finished product; it is quite acceptable to debug using test data or during animal experiments and remove the JTAG capability before use with human patients. Therefore all that is needed it to provide a way to disconnect JTAG while retaining the UART link which is useful when deployed, and a removable resistor array à la SCSI terminator resistors solves the problem neatly.

Or does it? One lurking issue here is that with two power sources, and the almost certainty of cycling power to the EPCS while connected to its debugger, these JTAG signals could be energized while their receiver is not. Such a situation threatens latch-up, as parasitic P-N junctions in the receiver IC provide a path to ground with very low incremental resistance and a low turn-on voltage on the order of 0.7V. The 3.3V which the FT2232H would drive onto the JTAG bus would be plenty high to induce latch-up in many chips. Using a resistor array with non-zero values, such as the 47-ohm SIP selected, helps mitigate the problem by limiting the maximum current. Ordinarily protection diodes would be added to the circuit as well to assure that any current passes through a safer route than the parasitic P-N junctions, but the ADuC702x datasheet indicates that these microcontrollers tolerate up to +5.3V on input pins irrespective of supplied power, and likewise with the FT2232H, so it seems this is a non-issue. (Note how other pins on both chips are rated with respect to V_CC or V_DD, but the digital inputs are not restricted.)

Here then is the completed circuit:

Admittedly a higher part count than just plunking down a 20-pin ARM-standard JTAG connector as shown in the ADUM702x datasheet example application circuit, but much more capable. In addition USB 2.0 high-speed capability used to make quite a statement, but now USB super-speed is preparing for debut and promises to quickly become the logo du jour.